Clock and data recovery (CDR) circuits may be implemented to allow a system to generate a clock signal, based on a received data signal, that is synchronized with the received data signal. CDR circuits may be implemented using analog or digital components. In some circumstances, a CDR circuit may be implemented using multiple different components formed on separate substrates that are coupled using a printed circuit board. In other circumstances, a CDR circuit may be implemented using circuitry formed on a single substrate.
A CDR circuit may also have an associated state machine that may indicate to the CDR circuit basic states of functionality. Some of the basic states of functionality may include, whether a data signal is being received and/or if the CDR circuit is locked onto a received data signal. Typically, the associated state machine provides a rigid structure that does not allow the CDR circuit to adapt to changing circumstances. Additionally, the state machine may be formed separately from the CDR circuit and coupled to the CDR circuit using a printed circuit board.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practiced